The invention relates to a method for setting an effective resolution of an output signal in an incremental delta-sigma analog-to-digital conversion by means of an incremental delta-sigma analog-to-digital converter, in which the difference between an input signal and a reference voltage signal formed in a feedback branch is fed to a first integrator.
The invention furthermore relates to an arrangement for incremental delta-sigma analog-to-digital conversion, wherein the incremental delta-sigma analog-to-digital converter comprises a difference forming unit for forming a difference between an analog modulator input signal and an analog reference voltage signal and for generating a difference voltage signal (u′in), a resettable first integrator for integrating or summing the difference signal and generating a first integrator signal (u1), a quantizer for receiving the integrator signal and generating a quantization signal, the bit stream, and a digital-to-analog converter in a feedback branch for receiving the digital quantization signal and outputting the reference voltage signal to the difference forming unit.
The prior art is constituted by incremental delta-sigma analog-to-digital converters (iDS-ADCs) of a wide variety of architectures in which an input signal to be converted is firstly modulated by a modulator loop for a certain, predefined clock cycle number N and the digital bit stream at the output of the internal quantizer is digitally filtered. The digital filter then outputs a digital representation of the analog input signal Uin after N clock cycles.
The prior art discloses some methods and arrangements which are utilized for avoiding or eliminating problems that occur with the use of incremental delta-sigma analog-to-digital converters.
U.S. Pat. No. 6,909,388 B1 discloses for example a method which can be used to isolate and compensate for the input offset of a sampled input signal for an analog-to-digital (A/D) conversion using incremental delta-sigma analog-to-digital converters. Using a fractal algorithm, for this purpose a sampling sequence is utilized by means of which the offset can be compensated for via a suitable, switched capacitance. Thus, in U.S. Pat. No. 6,909,388 B1, a reduction of the flicker noise component in the output signal also becomes possible besides the real-time offset compensation and the corresponding increase in the effective output dynamic range of the iDS-ADC. In addition, the method presented in U.S. Pat. No. 6,909,388 B1 is independent of a multiplicity of technological process parameter variations, e.g. resulting in component mismatch.
US 2008/0074303 A1 discloses a method for improving the stability and for increasing the input voltage range in multi-stage, incremental delta-sigma analog-to-digital converters. In that case, at the beginning of each new AD conversion, either at least one or a plurality of integrator stages are held in the reset state and are switched in only after the first loop pass according to a specific scheme, or all the integrator stages are initially in the reset state and are switched in stage by stage per loop pass or iteration. The corresponding integrator stages remain stable here, as does the total transfer of the iDS-ADC. With the reset initialization method according to US 2008/0074303 A1, it thus becomes possible to realize noise transfer functions (for short: NTFs) which, for larger iDS-ADC input voltage signals, would have resulted in an unstable behaviour of the ADC under certain circumstances. Consequently, it is possible to realize more aggressive NTFs or to process higher input voltage signal ranges with an iDS-ADC. Furthermore, by means of the method set out in US 2008/0074303 A1, the realization of higher-order iDS-ADCs is simplified in particular with regard to fulfilling the necessary stability criteria (e.g. at high levels of the input signal). The specific use of an iDS-ADC is substantiated in US 2008/0074303 A1, inter alia, by the fact that the latency of iDS-ADCs corresponds to only approximately half of the baseband sample period of the connected decimation filter, as a result of which, firstly, individual conversions, such as e.g. by means of successive approximation register (SAR) converters, become possible. This is advantageous for the use of such an ADC in such applications in which the energy demand per conversion is of primary importance or/and in which the ADC is intended, can or must repeatedly attain a quiescent state. This last is the case in multiplexed systems, for example, in which one and the same ADC is intended to process signals of different input sources. This is not possible to the same extent with traditional delta-sigma analog-to-digital converters, for example, but rather requires an increased control and time and energy expenditure.
In iDS-ADCs a switched-capacitance (for short: SC) arrangement is often used to process the input signal to be digitized and the required reference voltage. In order to reduce so-called mismatch errors as a result of the capacitances used and at the same time to minimize the phases required for charge transfer in such a circuit (sampling and charge transfer), US 2011/0163901 A1 proposes a method in which, by means of a capacitance array through a suitable selection and rotating allocation of different input capacitances during an A/D conversion, ultimately the mismatch influence and the gain error can be reduced. The method proposed in US 2011/0163901 A1 relates in that case to iDS-ADCs which operate using a chopped reference signal. According to US 2011/0163901 A1, the ratio of signal to reference (S/R) must therefore be less than 1 in order to ensure the stability in higher-order iDS-ADCs. In this context, it is possible to utilize the method described in US 2011/0163901 A1 for reducing mismatch and gain errors as it were ultimately also to achieve, by means of the capacitance array mentioned above, a damping of the input signal and thus: S/R<1 with the aim of modulator stability in iDS-ADCs with a chopped reference signal.
One specific realization of this method is explained in V. Quiquempoix et al.: “A Low-Power 22-bit Incremental ADC”, IEEE Journal of Solid-State Circuits, Vol. 41, No. 7, July 2006 wherein a 3rd order delta-sigma converter is used. An S/R ratio of 2/3 is striven for in order to obtain a differential input charge Qin of the iDS-ADC on the input capacitance Cin (depending on the input voltage Uin and the output voltage of the digital-to-analog converter (DAC) generated in the feedback path of the iDS-ADC: UDAC) wherein Qin=Cin (2/3·Uin−UDAC) holds true. Alongside the condition that S/R<1 must be the case in principle, V. Quiquempoix et al. also explain that the clock cycle number N for an A/D conversion in the iDS-ADC should be an integral multiple of the reference in order in turn not to generate any further gain errors in the iDS-ADC.
DE 102011079211 B3 describes a method and the realization thereof as an incremental delta-sigma analog-to-digital converter, in which the quantization error is determined by means of a specific minimum determination on the basis of the internally processed quantization noise dependent on the input signal in the iDS-ADC at the output of the (multi-stage) integrator stage chain. An improvement in the accuracy of the output signal or output value of the iDS-ADC is thus made possible in accordance with DE 102011079211 B3. Furthermore, DE 102011079211 B3 describes that in the context of the explained method for improving the accuracy of the ADC output value, a reset of the converter values can or should be realized before a new AD conversion. Furthermore DE 102011079211 B3 discloses that in the method a quantization noise signal is scaled by means of a propagation-time-dependent coefficient in order to perform an adaptation of the loop passes in the iDS-ADC with the correspondingly scaled signal. This adaptation of the loop passes is principally aimed at the highest possible accuracy of the ADC output value.
Incremental delta-sigma analog-to-digital converters typically process an analog input signal in order to assign a digital output signal that is as proportional as possible to said input signal or in order to realize a preferably unique mapping of the analog input signal onto a digital output word (FIG. 1).
Generally, the input signal is superimposed by broadband noise (thermal noise). There are a series of ADC-inherent noise sources, such as thermal noise of resistors or recombination noise of active components having a pn junction in the ADC circuit. In the case of delta-sigma-based converters, the output noise is often dominated by so-called quantization noise and the input noise is often dominated by flicker or 1/f noise. On account of noise shaping within a (both traditional and incremental) delta-sigma analog-to-digital converter, a large part of the quantization noise and of the thermal noise NIN of the input signal can be shifted towards higher frequencies by so-called noise shaping and can be filtered by means of a low-pass filter and removed from the signal to be digitized. However, signal components such as DC signal offsets or/and a large part of the flicker noise cannot be compensated for thereby. FIG. 2 shows an equivalent illustration of the incremental delta-sigma analog-to-digital converter from FIG. 1 as a time-discrete system, that is to say a system operating in a sampled manner. The input signal noise shall be NIN and the noise caused by the quantization shall be E.
An increase in the order of the modulator in the incremental delta-sigma analog-to-digital converter generally results in an increase in the accuracy of the ADC output value, wherein at the same time the implementation outlay rises and it becomes increasingly more difficult to ensure the stability of the modulator loop, or only small loop stability reserves can be realized. This in turn leads to a higher, undesired susceptibility of the modulator loops and thus of the ADC per se to disturbances. The increase in the modulator order likewise leads to a reduction of the input signal range processable in the incremental delta-sigma analog-to-digital converter, and thus to a reduction of the input dynamic range.
Incremental delta-sigma analog-to-digital converters differ from conventional delta-sigma ADCs in particular to the effect that the integrators are reset for each new A/D conversion and, consequently, there is a direct mapping of an input signal value onto exactly only one output signal value. This is advantageous, inter alia, for use in multiplexed systems having a plurality of input signal sources.
Every higher-order delta-sigma-modulator-based converter is restricted with regard to its stability to an input signal range (dynamic range) which corresponds to only part of the reference voltage used. Therefore, the input signal has to be damped, if appropriate, in order reliably to remain in the stable operating range of multi-stage iDS-ADCs. It is typical here that as the modulator order increases, the degree of damping with regard to the input signal also increases. However, this also results in an impairment of the input signal level available in the ADC, which in turn entails either a reduction in the accuracy of the digital output signal or an increase in the signal processing complexity in order to achieve the same output accuracy which could be obtained by such an ADC (without stability limitation). Furthermore, offsets in the input signal can lead to a further reduction in the dynamic range actually available for the useful signal component in the input signal. Such offsets should therefore be removed before the conversion in the iDS-ADC. For this purpose, either the method from the U.S. Pat. No. 6,909,388 B1 could be used, or an extended dynamic range with stable ADC behaviour should be provided.